1. Field of the Invention
The present invention relates to a method and device for driving plasma display panel.
2. Description of the Related Art
In recent years, to meet the increasing demand for thin-shape display panels as a result of widespread use of large screen display apparatus, various types of thin display panels have been realized. AC discharge type plasma display panels are one kind of flat panel display that has received considerable attention.
FIG. 1 is a schematic diagram of the construction of a plasma display apparatus comprising such a plasma display panel and a driving device for driving the same.
As shown in FIG. 1, the plasma display panel PDP 10 has m column electrodes D1 to Dm which are intersected by n row electrodes X1 to Xn and n row electrodes Y1 to Yn arranged so as to intersect to the former. A pair of these row electrodes X1 to Xn and Y1 to Yn comprising one row electrode Xi (1≦i≦n) and one row electrode Yi (1≦i≦n) correspond to a display line in the PDP 10. The row electrodes X and Y are arranged so as to intersect the column electrodes D, with a discharge space in between enclosing the discharge gas; the discharge cells corresponding to the pixels are formed in each point of intersection of the row electrode pairs and the column electrodes comprising this discharge space.
The discharge cells, which are light-emitting elements using discharge phenomena, can each be placed in only one of two states, i.d, light-on state and light-off state. That is, each of the discharge cells only displays luminance with two gradation levels, a minimum luminance (light-off state) and a maximum luminance (light-on state).
In the PDP 10 with such discharge cells, the driving device 100 carries out the gradation driving for implementing the halftone according to an input video signal by means of the subfield method. In the subfield method, each field in the input video signal is divided into 5 subfields SF1 to SF5, as shown in FIG. 2. The emission driving is performed in each of the subfields by allocating an emission period corresponding to the weighting of these subfields.
FIG. 3 is a diagram showing each of the driving pulses that the driving device 100 applies to the columns electrodes and row electrode pairs of the above PDP 10, and the respective application timings.
Firstly, in the general reset step Rc, the driving device 100 applies a positive reset pulse RPx to the row electrodes X1 to Xn, and a negative reset pulse RPy to the row electrodes Y1 to Yn. In response to these applied reset pulses RPx and RPy, all the discharge cells in PDP 10 undergo a reset discharge whereby in each discharge cell a predetermined quantity of wall charges are uniformly built. This way all the discharge cells are initialized into an emission enable state.
Next, in the address step Wc, the driving device 100 converts the inputted image signal for each pixel into 5-bit pixel data. It generates pixel data pulses having a pulse voltage corresponding to the logical level of the first bit of this pixel data for subfield SF1, the second bit for SF2, the third bit for SF3, the fourth bit for SF4 and the fifth bit for SF5. For instance, in subfield SF1, the driving device 100 generates a pixel data pulse having a pulse voltage corresponding to the logical level of the first bit of the above pixel data. Herein, if the logical level of the first bit is “1”, the driving device 100 generates a pixel data pulse having a high-voltage pulse; if the logical level of the first bit is “0”, it generates a pixel data pulse having a low-voltage (0 volt). The driving device 100 sequentially applies these pixel data pulses, to the column electrodes D1 to Dm, one display line at a time. That is, firstly, the driving device 100 applies the pixel data pulse group DP1, formed by the m pixel data pulses corresponding to the first display line, to the column electrodes D1 to Dm; next it applies the pixel data pulse group DP2, formed by the m pixel data pulses corresponding to the second display line, to the column electrodes D1 to Dm. Further, the driving device 100, in synchronization with the application timing of each pixel data pulse group DP, generates negative scanning pulses SP and applies them in succession to the row electrodes Y1 to Yn, as shown in FIG. 3. Now, discharges (selective erasing discharges) take place only in those discharge cells in the intersection points of the column electrodes to which high-voltage pixel data pulses have been applied and the display lines to which the scanning pulses SP have been applied, whereby the wall charges formed inside the discharge cells erase. Thus the discharge cells initialized into an emission enable state in the above general reset step Rc change to a state wherein they cannot emit (hereinafter referred to as the emission disable state) in the emission sustain step Ic described below. On the other hand, although they have been applied a scanning pulse SP, the above selective erasing discharge does not occur in the discharge cells having been applied a low-voltage pixel data pulse, and they continue in the initialized state as per the above general reset step Rc, that is, in an emission enable step.
So, by means of the address step Wc, either one or the other of the following states is set for each of the discharge cells in PDP 10 in response to pixel data corresponding to an input pixel data; either an emission enable state in the emission sustain step Ic, or an emission disable state in the emission sustain step Ic.
Further, in the address step Wc, the driving device 100 sequentially applies positive priming pulses PP to the row electrodes Y1 to Yn immediately preceding the scanning pulses SP, as shown in FIG. 3. By applying these priming pulses, a priming discharge is made to occur in the discharge cells in order for priming particles to form in the discharge spaces. Thus, in order for the selective erasing discharge to be effectively carried out, sufficient priming particles are left in the discharge spaces of each discharge cell prior to the selective erasing discharge.
Next, in the emission sustain step Ic, the driving device 100 repeatedly applies positive sustain pulses IPx and IPy to the row electrodes X1 to Xn and Y1 to Yn throughout the period allocated in each of the above subfields. Now, only those discharge cells in whose discharge space a residual wall charge remains, i.e. those cells in an emission enable state, discharge (sustain discharge) whenever they are applied these sustain pulses IPx and IPy. That is, only those discharge cells where no selective erasing discharge occurred in the above address step Wc maintain their emission state by repeating the emission brought about by the above sustain discharge, throughout the period allocated in each of the above subfields.
Then, in the erasing step E, the driving device 100 applies simultaneously an erasing pulse EP to the row electrodes Y1 to Yn, as shown in FIG. 3. By applying this erasing pulses EP, an erasing discharge is made to take place in all the discharge cells of PDP 10, thereby erasing the remaining wall charges in the discharge cells.
The above general reset step Rc, address step Wc, emission sustain step Ic and erasing step E are performed in succession for each of the subfields SF1 to SF5 shown in FIG. 2. By means of such driving, emission is achieved through the sustain discharges extending through the emission periods corresponding to the luminance level of the input video signal, wherein luminance is perceived in accordance with those emission periods. In this case, for the subfields SF1 to SF5 shown in FIG. 2, there are 52=32 possible subfield combination patterns for causing emission, with a different total sum of emission periods per subfield. By means of a drive based on these 5 subfields SF1 to SF5, therefore, an intermediate luminance of 32 gradation levels can be displayed.
However, in the drive scheme described above, problems of low image display contrast arise, since the discharges for emission are made to occur in each subfield without any reference to the display image, like the above reset discharge and erasing discharge.